PIC microcontroller - Wikipedia, the free encyclopedia. PIC microcontrollers in DIP and QFN packages. PDIP PIC2. 4 microcontroller next to a metric ruler. PIC is a family of microcontrollers made by Microchip Technology, derived from the PIC1. The name PIC initially referred to Peripheral Interface Controller. All current models use Flash memory for program storage, and newer models allow the PIC to reprogram itself. Program memory and data memory are separated. Data memory is 8- bit, 1. Program instructions vary in bit- count by family of PIC, and may be 1. The instruction set also varies by model, with more powerful chips adding instructions for digital signal processing functions. The hardware capabilities of PIC devices range from 8- pin DIP chips up to 1. SMD chips, with discrete I/O pins, ADC and DAC modules, and communications ports such as UART, I2. C, CAN, and even USB. Low- power and high- speed variations exist for many types. The manufacturer supplies computer software for development known as MPLAB, assemblers and C/C++ compilers, and programmer/debugger hardware under the MPLAB and PICKit series. Third party and some open- source tools are also available. Some parts have in- circuit programming capability; low- cost development programmers are available as well has high- production programmers. PIC devices are popular with both industrial developers and hobbyists due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, serial programming, and re- programmable Flash- memory capability. History. Whilst most people considered the CP1. CPU, it had poor I/O performance, and the 8- bit PIC was developed in 1. I/O tasks from the CPU. 7 Getting Startred: I2C Master Mode The PIC used simple microcode stored in ROM to perform its tasks, and although the term RISC was not used at the time, it shares some common features with RISC designs. In 1. 98. 5, General Instrument sold their microelectronics division and the new owners cancelled almost everything . The PIC, however, was upgraded with an internal EPROM to produce a programmable channel controller. Today, a huge variety of PICs are available with various on- board peripherals (serial communication modules, UARTs, motor control kernels, etc.) and program memory from 2. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1. PIC1. 65. 0 devices was . The baseline and mid- range families use 8- bit wide data memory, and the high- end families use 1. The latest series, PIC3. MX is a 3. 2- bit MIPS- based microcontroller. Instruction words are in sizes of 1. PIC1. 0 and PIC1. PIC1. 6) and 2. 4- bit (PIC2. PIC). The binary representations of the machine instructions vary by family and are shown in PIC instruction listings. PIC1. 0 and PIC1. They are represented by the PIC1. PIC1. 2 and PIC1. Baseline devices are available in 6- pin to 4. Generally the first 7 to 9 bytes of the register file are special- purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 1. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high- order bits are taken from the status register. Before we get to the nitty gritty of programming the PIC. Programming PIC Microcontrollers Module: EE2A2 Embedded Microprocessor Systems. CPU Program and data memory Harvard Architecture: Program CPU Data. Kernighan and Ritchie say in the Introduction of The C Programming Language: 'C. The program prints 'hello. It allows users to easily develop for Microchip's PIC. The Academic Program demonstrates Microchip's on-going commitment to education by offering unique. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 5. Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions. This . These devices are available in 6- pin and 8- pin packages (with two pins unused). Input only and 3 I/O pins are available. A complex set of interrupts are available. Clocks are an internal calibrated high- frequency oscillator of 1. MHz with a choice of selectable speeds via software and a 3. Hz low- power source. These devices feature a 1. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 1. There are a few additional miscellaneous instructions, and two additional 8- bit literal instructions, add and subtract. The mid- range core is available in the majority of devices labeled PIC1. PIC1. 6. The first 3. RAM. If banked RAM is used, the high 1. The 1. 7 series is not recommended for new designs, and availability may be limited. Improvements over earlier cores are 1. PIC1. 7 devices were produced in packages from 4. The 1. 7 series introduced a number of important new features. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language. They are saved on every interrupt, and may be restored on return. If interrupts are disabled, they may also be used on subroutine call/return by setting the s bit (appending . Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR. In more advanced PIC1. If FSR2 is used either as the stack pointer or frame pointer, stack items may be easily indexed. Microchip's MPLAB C1. C compiler chooses to use FSR2 as a frame pointer. PIC2. 4 and ds. PIC. They are Microchip's first inherently 1. PIC2. 4 devices are designed as general purpose microcontrollers. Software can access ROM in 1. The high half of odd words reads as zero. The program counter is 2. Instructions come in two main varieties, with most important operations (add, xor, shifts, etc.) allowing both forms. The first is like the classic PIC instructions, with an operation between a specified f register (i. The destination and one of the sources also support addressing modes, allowing the operand to be in memory pointed to by a W register. PIC3. 2M MIPS- based line. Their instruction set is nothing like the Microchip- designed single- operand instruction sets of earlier PIC processors, but use the MIPS instruction set, with 3. Von Neumann architecture. PIC3. 2MX. The first 1. PIC3. 2MX3xx and PIC3. MX4xx) are pin to pin compatible and share the same peripherals set with the PIC2. Fxx. GA0xx family of (1. Today, starting at 2. QFN packages up to high performance devices with Ethernet, CAN and USB OTG, full family range of mid- range 3. The PIC3. 2 architecture brought a number of new features to Microchip portfolio, including: The highest execution speed 8. MIPS (1. 20+. The PIC3. MZ series include. Special- purpose control registers for on- chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory. Later series of devices feature move instructions, which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved through the accumulator. To implement indirect addressing, a . A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP). External data memory is not directly addressable except in some PIC1. Code space. In general, there is no provision for storing code in external memory due to the lack of an external memory interface. The exceptions are PIC1. PIC1. 8 devices. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC1. PIC1. 6) families have program memory addressable in the same wordsize as the instruction width, i. In contrast, in the PIC1. In order to be clear, the program memory capacity is usually stated in number of (single- word) instructions, rather than in bytes. PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software- accessible on earlier devices, but this changed with the 1. Hardware support for a general- purpose parameter stack was lacking in early series, but this greatly improved in the 1. Instruction set. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching. Some operations, such as bit setting and testing, can be performed on any numbered register, but bi- operand arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the . The skip instructions are . Because cores before PIC1. Skips are also of utility for conditional execution of any immediate single following instruction. It is possible to skip skip instructions. For example, the instruction sequence . One instruction peculiar to the PIC is retlw, load immediate into WREG and return, which is used with computed branches to produce lookup tables. Operation with WREG and indexed register. The result can be written to either the Working register (e. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as . Other than the skip instructions previously mentioned, there are only two: goto and call.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. Archives
December 2016
Categories |